NAME VGA_TIMING_800x600;
PARTNO ATF1504AS;
DATE 07-12-2025;
REVISION 14;
DESIGNER Lev Vayner;
COMPANY Vayner Systems;
ASSEMBLY DUAL BUFFER VGA;
LOCATION U1;
Device f1504ispplcc44;

/* MCU Ready Input, active low */
Pin 1 = RDY;
/* Clock input */
Pin 2 = CLK;

/* Horizontal Counter (10-bit) */
Pin 4  = HC0;
Pin 5  = HC1;
Pin 6  = HC2;
Pin 8  = HC3;
Pin 9  = HC4;
Pin 11 = HC5;
Pin 12 = HC6;
Pin 14 = HC7;
Pin 16 = HC8;
Pin 17 = HC9;

/* Vertical Counter (10-bit) */
Pin 18 = VC0;
Pin 19 = VC1;
Pin 20 = VC2;
Pin 21 = VC3;
Pin 24 = VC4;
Pin 25 = VC5;
Pin 26 = VC6;
Pin 27 = VC7;
Pin 28 = VC8;
Pin 29 = VC9;

/* Output signals */
Pin 33 = HSYNC;
Pin 34 = VSYNC;
PIN 36 = MCU_BANK_SELECT;
Pin 39 = V_OUT;

PINNODE 81 = RDY_1;
PINNODE 86 = RDY_LATCH;
PINNODE 87 = VC_IS_599;
/* ---------------- Horizontal Counter (0-1023, should be 1056, cheating a bit, monitor should allow it ) ---------------- */
HC0.d  = !HC0;
HC0.ck = CLK;

HC1.d  = HC1 $ HC0;
HC1.ck = CLK;

HC2.d  = HC2 $ (HC1 & HC0);
HC2.ck = CLK;

HC3.d  = HC3 $ (HC2 & HC1 & HC0);
HC3.ck = CLK;

HC4.d  = HC4 $ (HC3 & HC2 & HC1 & HC0);
HC4.ck = CLK;

HC5.d  = HC5 $ (HC4 & HC3 & HC2 & HC1 & HC0);
HC5.ck = CLK;

HC6.d  = HC6 $ (HC5 & HC4 & HC3 & HC2 & HC1 & HC0);
HC6.ck = CLK;

HC7.d  = HC7 $ (HC6 & HC5 & HC4 & HC3 & HC2 & HC1 & HC0);
HC7.ck = CLK;

HC8.d  = HC8 $ (HC7 & HC6 & HC5 & HC4 & HC3 & HC2 & HC1 & HC0);
HC8.ck = CLK;

HC9.d  = HC9 $ (HC8 & HC7 & HC6 & HC5 & HC4 & HC3 & HC2 & HC1 & HC0);
HC9.ck = CLK;
/* Wrap signals for horizontal and vertical lines */
H_WRAP = HC9 & HC8 & HC7 & HC6 & HC5 & HC4 & HC3 & HC2 & HC1 & HC0;
V_WRAP = VC9 & VC6 & VC5 & VC3 ;

/* ---------------- Vertical Counter (limit 628) ---------------- */
VC0.d = (VC0 $ (H_WRAP # V_WRAP)) & !V_WRAP;
VC0.ck = CLK;

VC1.d = (VC1 $ (VC0 & H_WRAP)) & !V_WRAP;
VC1.ck = CLK;

VC2.d = (VC2 $ (VC1 & VC0 & H_WRAP)) & !V_WRAP;
VC2.ck = CLK;

VC3.d = (VC3 $ (VC2 & VC1 & VC0 & H_WRAP)) & !V_WRAP;
VC3.ck = CLK;

VC4.d = (VC4 $ (VC3 & VC2 & VC1 & VC0 & H_WRAP)) & !V_WRAP;
VC4.ck = CLK;

LOW5 = VC4 & VC3 & VC2 & VC1 & VC0 & H_WRAP;

VC5.d = (VC5 $ LOW5) & !V_WRAP;
VC5.ck = CLK;

VC6.d = (VC6 $ (VC5 & LOW5)) & !V_WRAP;
VC6.ck = CLK;

VC7.d = (VC7 $ (VC6 & VC5 & LOW5)) & !V_WRAP;
VC7.ck = CLK;

VC8.d = (VC8 $ (VC7 & VC6 & VC5 & LOW5)) & !V_WRAP;
VC8.ck = CLK;

VC9.d = (VC9 $ VC8 & VC7 & VC6 & VC5 & LOW5) & !V_WRAP;
VC9.ck = CLK;


/* ---------------- Output Signals ---------------- */

/* HSYNC: active low from HC = 832 to 959 (approx) */
HSYNC = !(HC9 & HC8 & !HC7);

/* H_VIDEO_OUT: active when HC < 800, V_VIDEO_OUT < 600 */
H_VIDEO_OUT = !(HC9 & HC8) # (!HC7 & !HC6 & !HC5);
V_VIDEO_OUT= !VC9 # ( !VC8 & !VC7 & (!VC6 # !VC4));

/* VSYNC: active low during VC = 601-604 */
VSYNC = !(VC9 & VC6 & VC4 & VC3 & !VC2);
/* Composite video enable, active LOW */
V_OUT = !(H_VIDEO_OUT & V_VIDEO_OUT);


/* Generate toggle of memory banks when READY input goes high. flip after visible area */
/* Last RDY state */
RDY_1.d = RDY;
RDY_1.ck = CLK;

/* Rising edge pulse */
RDY_R = RDY & !RDY_1;

VC_IS_599 = VC9 & !VC7 & VC6 & !VC5 & VC4 & !VC3 & VC2 & VC1 & VC0;

/* Latch RDY_R until VC_IS_599 comes */
RDY_LATCH.d = RDY_R # (RDY_LATCH & !VC_IS_599);
RDY_LATCH.ck = CLK;

/* Final toggle condition */
TOGGLE_COND = RDY_LATCH & VC_IS_599;

/* Toggle MCU_BANK_SELECT */
MCU_BANK_SELECT.d = MCU_BANK_SELECT $ TOGGLE_COND;
MCU_BANK_SELECT.ck = CLK;